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AR# 29356

CPLD CoolRunner-II - Incorrect values on global function pins during JTAG SAMPLE instruction


The JTAG SAMPLE operation that reads the state of I/O pins (this includes EXTEST and INTEST) does not read the proper values on global function pins* in specific pin configurations.

Devices Affected: XC2C32, XC2C32A, XC2C64, XC2C64A. Other CoolRunner-II densities are NOT affected

* The global function pins are Global Clock(GCK), Global Set Reset(GSR), Global Output Enable.

This behavior is NOT observed in the following cases:

- the device is erased

- these pins are used as general purpose I/O

- these pins have Schmitt Trigger enabled


The simplest fix is to apply Schmitt Trigger on the Global function pins in use. The only potential issue is that there is a time delay adder for an input using Schmitt Trigger. This value is specified as ThysXX in the device data sheet and ranges from 1.0 to 4.0 nS depending on the device and the I/O Standard.

This attribute is applied in the UCF, as shown in the following example:

Net my_global_input Schmitt_trigger;

If the design cannot tolerate the delay by using Schmitt Trigger on these pins, ask Xilinx Technical Support to edit the JEDEC programming file as a work-around for this issue. This work-around does not remove any resources that could have been used and does not affect the design functionality.

AR# 29356
Date Created 10/28/2007
Last Updated 12/15/2012
Status Active
Type General Article