We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 29418

9.2i EDK, Spartan-3A DSP - "ERROR:Place:848 - Automatic clock placement failed"


Keywords: BSB, DCM, Spartan, 500, BUFG, DSP, PAR, MAP, timing

When I create a Base System Builder (BSB) design for the Spartan-3A DSP, the following error occurs:

"ERROR:Place:848 - Automatic clock placement failed. Please attempt to analyze the global clocking required for this design and either lock the clock placement or area locate the logic driven by the clocks so that the clocks may be placed in such a way that all logic driven by them may be routed. The main restriction on clock placement is that only one clock output signal for any competing Global / Side pair of clocks may enter any region. For further information see the "Quadrant Clock Routing" section in the Spartan-3adsp Family Data Sheet."


To work around this issue, do not use the -timing MAP switch. To turn off this switch, follow these steps:

1. In XPS, bring the Project tab forward.
2. Under Project Files, double-click on the fast_runtime.opt file.
3. Find the Program MAP section and delete -timing.
4. Save and close the fast_runtime.opt file.
AR# 29418
Date Created 10/28/2007
Last Updated 09/26/2007
Status Active
Type General Article