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AR# 29431

9.1i ISE - Project Navigator fails to create a timing simulation netlist for an EDIF project


Keywords: NetGen, Post-Place&Route, EDN, delimiter, space, parser, DU, top, Design Compiler, TMRTool, generate

An EDIF file is successfully added to a project as the top-level file and can be implemented. However, creating the timing netlist fails.
When the "Generate Post-Place&Route Simulation Model" process is run, NetGen starts but fails with no apparent error or warning.


This problem can occur if the EDIF file does not have a space (any white space) after the design name. The Project Navigator EDIF parser incorrectly processes EDIFs in which there is no delimiter before a parenthesis. Specifically, structures such as the following cause Project Navigator to incorrectly process the top-level entity name as "TOP_MOD(" instead of TOP_MOD.

(design TOP_MOD(cellRef TOP_MOD (libraryRef work_tmr ))

Your design can still be implemented with Project Navigator. However, NetGen cannot be run from ISE because the NCD file with the perceived top module name ("TOP_MOD(.ncd" in the example above) does not exist.

In this case, the module name throughout the ISE GUI is incorrect.

NOTE: The lack of white space before a parenthesis is valid EDIF. Delimiters can occur on either side of parentheses in EDIF forms, but are not required. EDIF delimiters are the ASCII characters space, tab, carriage-return, and line-feed.

EDIF files with this structure generated from some versions of the Xilinx TMRTool and Synopsys Design Compiler have been observed.

To work around this issue, you can either edit the EDIF file to add the white space that the Project Navigator parser is looking for or run NetGen from the command line to generate the simulation netlist.

This problem has been fixed in the latest 9.2i Service Pack available at:
The first service pack containing the fix is 9.2i Service Pack 4.
AR# 29431
Date Created 10/28/2007
Last Updated 04/17/2009
Status Archive
Type General Article