We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 29443

MIG v2.0 - Virtex-5 DDR2 calibration debug port signal descriptions


Starting with MIG v2.0, the Virtex-5 DDR2 interface HDL adds a port to the top-level design file to allow debug and monitoring of the physical layer read timing calibration logic and timing. This port consists of signals brought to the top-level HDL from the PHY_CALIB_0 module (where the read timing calibration logic resides). These signals provide information in debugging hardware issues when calibration does not complete or read timing errors are observed in the system even after calibration completes. They also allow the user to adjust the read capture timing by adjusting the various IDELAY elements used for data synchronization.

Specifically, the Debug Port allows the user to:

  • Observe calibration status signals
  • Observe current values for IDELAYs used for read data synchronization
  • Dynamically vary these IDELAY values. Possible uses of this functionality include:
    • Debug read data corruption issues
    • Support periodic readjustment of the read data capture timing by adjusting the IDELAY values
    • Use as a tool during product margining to determine actual timing margin available on read data capture

This answer record details the following:

  • Enabling the Debug Port
  • Debug Port Clocking
  • Signal Descriptions
  • Adjusting IDELAY Taps
  • Sample Control/Monitoring of the Debug Port

This information will be included in the v2.1 MIG User Guide.


Starting with the release of MIG 2.1, this information is available in the MIG User Guide. Please see the MIG User Guide for further information.

Enabling the Debug Port

The Debug Port is enabled by setting the top-level HDL parameter DEBUG_EN to 1. To disable the Debug Port, set DEBUG_EN to 0. This prevents the synthesis of additional logic required to support the Debug Port (e.g., logic to allow dynamic adjustment of the IDELAY taps).

Debug Port Clocking

All debug port signals are clocked using the half-frequency clock (CLKDIV) in the DDR2 design. Increment and decrement control signals (e.g., DBG_IDEL_UP_ALL) must be provided synchronously with CLKDIV. IDELAY select signals, such as DBG_SEL_ALL_IDEL_DQS and DBG_SEL_IDEL_DQS may change asynchronous to CLKDIV, but must meet setup and hold requirements on CLKDIV on cycles when the corresponding increment/decrement control signal is asserted.

Signal Descriptions

The Debug Port signals are described in aPDF located at:


Adjusting IDELAY Taps

The Debug Port can be used for dynamic adjustment of IDELAY taps. This can be initiated either through a Xilinx Virtual I/O (VIO) module, or through other custom control logic.

The procedure for adjusting the IDELAY taps is as follows:

1. If all IDELAY taps used in the DDR2 Interface (for all DQ, DQS, and DQS Gate) must be adjusted at once:

  • Assert either DBG_SEL_IDEL_UP_ALL or DBG_SEL_IDEL_DOWN_ALL. For every CLKDIV cycle, one or the other of these two signals is asserted, the IDELAY taps are incremented or decremented by 1. In general, when using VIO to control these signals, the user will want to make sure these control outputs are set to generate a single pulse one clock cycle wide when selected, in order to exactly control the amount of adjustment.

2. If all DQ IDELAYs must be adjusted at once:

  • Use DBG_IDEL_UP_DQ or DBG_IDEL_DOWN_DQ to either increment or decrement all DQ IDELAYs at once. As is the case with DBG_SEL_IDEL_UP_ALL, these control signals will increment or decrement the IDELAY tap count by 1 for every CLKDIV cycle they are asserted.

3. If only a specific DQ IDELAY must be adjusted:

  • Set DBG_SEL_IDEL_DQ to indicate the specific DQ IDELAY that will be adjusted. For example: for a 32-bit DDR2 interface, where DQ[10] must be adjusted, the user would set DBG_SEL_IDEL_DQ[4:0] = 010102.
  • Use DBG_IDEL_UP_DQ or DBG_IDEL_DOWN_DQ to either increment or decrement only the specified DQ IDELAY.

4. The procedure for adjusting all or individual DQS or DQS Gate IDELAY tap values is the same as outlined in (2) and (3) above, except that separate ports are provided for DQS and DQS Gate IDELAY adjustment.

Sample Control/Monitoring of the Debug Port

HDL code showing an example use of the Virtex-5 DDR2 Debug Port is included with this Answer Record. This example uses VIO cores generated using ChipScope Pro to both monitor the calibration status and IDELAY tap values, as well as allow dynamic adjustment of the IDELAY tap values. The zip file contains RTL, UCF, and ChipScope files for an example build using the Debug Port along with a README file explaining the contents, file structure, and how to build the design. Please download the example from:


AR# 29443
Date Created 10/28/2007
Last Updated 12/15/2012
Status Active
Type General Article
  • Virtex-5 FXT
  • Virtex-5 LX
  • Virtex-5 LXT
  • More
  • Virtex-5 SXT
  • Virtex-5 TXT
  • Less
  • MIG