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AR# 29462

10.1 EDK - Timing simulation testbench fails to compile for designs with MGT

Description

I have a design on a Virtex-4 FX device with the MGT protector IP. When compiling the models for simulation, the compiler errors out because of port mismatches in the MGT. Why does this happen?

Solution

For designs with MGTs, the system timing model contains extra ports that do not exist in the MHS. The test bench generated by SimGen does not define these extra ports. When compiling the models for simulation, the compiler errors out as a result of port mismatches. 

 

To work around this issue, remove the MGT Protector from design when using it for simulation purposes. The MGT protector IP is a very simple IP created to take care of the NBTI issue. The IP is required only in hardware.

AR# 29462
Date Created 10/28/2007
Last Updated 05/22/2014
Status Archive
Type General Article