I have a design in which a DCM is driving two BUFGs for clk0 and clk90. There are no timing errors or warnings in PAR, but the design does not work.
PAR can place one of the BUFGs far away from the DCM on Base System Builder designs using standard or Xplorer flows. This causes unpredictable skew between CLK0 and CLK90, and the design will not work correctly.
A PAR tactical patch has been created to address some of these problems for ISE 9.2i Service Pack 3:
1. Download the patch required for your platform:
2. Extract the zip file on the drive where Xilinx is installed (the Xilinx software should be installed in a folder named "Xilinx".)
This problem will be fixed in ISE 9.2i Service Pack 4, scheduled for release in December 2007.
If the problem persists after applying the patch to ISE 9.2i SP3 or installing ISE 9.2i SP4, you can work around this issue by manually placing the DCM and BUFGs in the design. For the Spartan-3E 1600 boards, this problem occurs mainly in the TEMAC Core. The clock resources and their locations are available in the Spartan-3E and Spartan-3A DSP User Guides: