LogiCORE Endpoint Block for PCI Express v1.6 - Release Notes and Known Issues for 9.2i IP Update 2
Description
Keywords: CORE Generator, ISE, installation, IP, update, PCIe, block, plus, hard block, integrated block, 9.2i_IP2
This Release Note and Known Issues Answer Record is for the LogiCORE Endpoint Block for PCI Express v1.6 released in 9.2i IP Update 2. It contains the following:
- General Information
- New Features
- Bug Fixes
- Known Issues
For installation instructions, general CORE Generator known issues, and design tools requirements, see (Xilinx Answer 29185).
Solution
General InformationAs of 9.2i sp 3 IP Update 2 Release, the LogiCORE Endpoint Block for PCI Express requires a license to generate and implement the core. There is no charge for this license. To obtain the license, visit the product lounge at:
http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.jsp?iLanguageID=1&sGlobalNavPick=&sSecondaryNavPick=&key=V5_PCI_Express_Block
Enhancements
- None
Bugs Fixed
-CR : 443758 "ModelSim simulation script forces user to change default resolution to ps" fixed
- CR : 447125 Endpoint block example design uses SOP and EOP signals when they should actually be unused and tied off
Known Issues
- Example Design: No split transactions. Completer cannot break a read request into two or more separate completions.
- Example Design: Can only process packets in VC0 and only on traffic class 0.
- Example Design: Endpoint does not initiate traffic without further modifications to the code.
- Some 250 MHz designs might not meet timing. Introducing area constraints and maxdelay constraints in the ucf might help the design to meet timing.