We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 29473

LogiCORE Initiator/Target v5.164 for PCI-X - Release Notes and Known Issues for 9.2i IP Update 2 (9.2i_IP2)


This Release Note and Known Issues Answer Record is for the LogiCORE Initiator/Target v5.164 for PCI-X released in 9.2i IP Update 2 and contains the following information:

- General Information

- New Features

- Bug Fixes

- Known Issues

For installation instructions, general CORE Generator known issues, and design tools requirements, see (Xilinx Answer 29185).


General Information

The LogiCORE PCI v5.164 supports Virtex-4, Virtex-II Pro, and Virtex-E architectures only. For Virtex-5 devices, use the v6.5 PCI-X Core. For more information on this core, refer to (Xilinx Answer 29474).

- See (Xilinx Answer 22921) for general information regarding timing closure in Virtex-4 devices.

New Features

- ISE 9.2i SP3 software support

Resolved Issues

- Issue: Faulty IRDY# disconnect sequence in PCI-X mode when the latency timer expires close to an ADB in the absence of GNT#

- Fixed: v5.1.164

- CR 447306: The logic on IRDY# has been corrected so that signal assertion is properly extended to the following ADB if the latency timer expires within three data phases of the next ADB.

Known Issues

The following are known issues for v5.1.164 of this core at time of release:

- None

AR# 29473
Date 12/15/2012
Status Active
Type General Article
Page Bookmarked