We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 29474

LogiCORE Initiator/Target v6.5 for PCI-X - Release Notes and Known Issues for 9.2i IP Update 2 (9.2i_IP2)


This Release Note and Known Issues Answer Record is for the LogiCORE Initiator/Target v6.5 for PCI-X released in 9.2i IP Update 2, and contains the following information:

- General Information

- New Features

- Bug Fixes

- Known Issues

For installation instructions, general CORE Generator known issues, and design tools requirements, see (Xilinx Answer 29185).


General Information

The LogiCORE PCI v6.5 supports Virtex-5 and newer architectures only. For all other devices, use the v5.164 PCI-X Core. For more information on this core, refer to (Xilinx Answer 29473).

New Features

- ISE 9.2i SP3 software support

- X5VSX95T support

Resolved Issues

- Virtex-5 pinouts reversed from order in standard plug-in connector

- Version Fixed: 6.5

- CR 444730: "ERROR:Timing:3369 - The configured internal frequency for CMB 'XPCI_WRAP/XPCI_PLL' exceeds the max frequency of 1000.000000 MHz" in Virtex-5 PCI-X 133 MHz mode

- Version Fixed: 6.5

- CR 447192: The CLKFBOUT_MULT and CLKOUT0_DIVIDE constraints on the PLL block have been adjusted to reduce the maximum internal frequency.

Known Issues

The following are known issues for v6.5 of this core at time of release:

- None

AR# 29474
Date 12/15/2012
Status Active
Type General Article
Page Bookmarked