We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 29475

LogiCORE UCF Generator v2.5 for PCI/PCI-X - Release Notes and Known Issues for 9.2i IP Update 2 (9.2i_IP2)


This Release Note and Known Issues Answer Record is for the LogiCORE PCI/PCI-X UCF Generator v2.5 released in 9.2i IP Update 2, and contains the following information:

- General Information

- New Features

- Bug Fixes

- Known Issues

For installation instructions, general CORE Generator known issues, and design tools requirements, see (Xilinx Answer 29185).


New Features

- ISE 9.2i SP3 software support

Resolved Issues

- CR 444730: Virtex-5 pin-outs reversed from order in standard plug-in connector. Fixed in v2.5.

- CR 447192: "ERROR:Timing:3369 - The configured internal frequency for CMB 'XPCI_WRAP/XPCI_PLL' exceeds the max frequency of 1000.000000 Mhz" in Virtex-5 PCI-X 133 MHz mode. Fixed in v2.5.

- The CLKFBOUT_MULT and CLKOUT0_DIVIDE constraints on the PLL block have been adjusted to reduce the maximum internal frequency.

Known Issues

- None

AR# 29475
Date Created 10/28/2007
Last Updated 12/15/2012
Status Active
Type General Article