MIG v2.0 - Virtex-5 DDR2 SDRAM Simulation Known Issues

AR#	29478	Search For Another Answer
Topic	MIG
Last Updated	06/14/2011
Status	Active

Description

When simulating the MIG v2.0 Virtex-5 DDR2 SDRAM design using ModelSim, the following problems might be encountered: 

• Fatal out-of-bounds index error occurs when running a VHDL simulation.  
• Incorrect data mask behavior and fatal error when simulating a 144-bit design with ECC enabled.  

This answer record contains a work-around for each of these issues.

Solution

Fatal out-of-bounds index error occurs when running VHDL simulation of Virtex-5 DDR2 design.  

Cause:  

Within the PHY_CALIB.VHD file, signal NEXT_COUNT_DQS is used as an index for various arrays of length DQS_WIDTH. This signal is used to track the current DQS being calibrated during the second stage of read data timing calibration. After completing this stage of calibration, NEXT_COUNT_DQS is incremented a final time. This causes an out-of-bounds index error in VHDL, as NEXT_COUNT_DQS is not larger than the array size of the element it references. This error can occur in one of two cases:  

• If the top-level parameter SIM_ONLY is set to 1, this error occurs only if the design has a single DQS (DQS_WIDTH=1);  
• If the top-level parameter SIM_ONLY is set to 0, the error occurs if the design has DQS_WIDTH = (power of 2). Note that this issue pertains only to VHDL simulation and should not affect hardware synthesis; the extra incrementation of NEXT_COUNT_DQS does not have any effect, as it happens at the end of stage 2 of calibration (and any "downstream" results are not used after stage 2 of calibration).  

Work-around: 

NEXT_COUNT_DQS should be prevented from being incremented one last time at the end of stage 2 calibration. The following changes should be made: 

Replace lines 1492-1505 with: 

if (cal2_detect_edge = '1') then 


cal2_curr_sel <= '1'; 

-- next_count_dqs <= count_dqs + 1; -- Prevent "extra" incrementation of NEXT_COUNT_DQS 

cal2_state <= CAL2_DONE; 

-- set all DQS groups to be the same for simulation  

if (SIM_ONLY /= 0) then 

cal2_rd_data_sel <= (others => '1'); 

else 

cal2_rd_data_sel(TO_INTEGER(count_dqs)) <= '1'; 

end if; 

if ((count_dqs = TO_UNSIGNED(DQS_WIDTH-1,DQS_BITS_FIX)) or 

(SIM_ONLY /= 0)) then 

calib_done_tmp(1) <= '1'; 

else 

next_count_dqs <= count_dqs + 1; -- Prevent "extra" incrementation of NEXT_COUNT_DQS  

end if; 

Replace lines 1526-1539 with: 

if (cal2_detect_edge = '1') then 


cal2_curr_sel <= '0'; 

-- next_count_dqs <= count_dqs + 1; -- Prevent "extra" incrementation of NEXT_COUNT_DQS 

cal2_state <= CAL2_DONE; 

-- set all DQS groups to be the same for simulation  

if (SIM_ONLY /= 0) then 

cal2_rd_data_sel <= (others => '0'); 

else 

cal2_rd_data_sel(TO_INTEGER(count_dqs)) <= '0'; 

end if; 

if ((count_dqs = TO_UNSIGNED(DQS_WIDTH-1,DQS_BITS_FIX)) or 

(SIM_ONLY /= 0)) then 

calib_done_tmp(1) <= '1'; 

else 

next_count_dqs <= count_dqs + 1; -- Prevent "extra" incrementation of NEXT_COUNT_DQS 

end if; 

Replace lines 1546-1552 with: 

cal2_idel_dec_cnt <= ('0' & cal2_idel_tap_limit(5 downto 1)); 


cal2_state <= CAL2_DEC_IDEL; 

-- next_count_dqs <= count_dqs + 1; -- Prevent "extra" incrementation of NEXT_COUNT_DQS 

if ((count_dqs = TO_UNSIGNED(DQS_WIDTH-1,DQS_BITS_FIX)) or 

(SIM_ONLY /= 0)) then 

calib_done_tmp(1) <= '1'; 

else 

next_count_dqs <= count_dqs + 1; -- Prevent "extra" incrementation of NEXT_COUNT_DQS  

end if; 

Incorrect data mask behavior and fatal error when simulating a 144-bit design with ECC enabled 

Cause: 

The ECC widths are not calculated correctly in the design. This causes simulation errors. 

Work-around:  

Replace the following lines of code with the code provided: 

Verilog - Edit phy_write.v 

Replace lines 282 and 283 with: 

wdf_mask_r <= {&wdf_mask_data[34:27], wdf_mask_data[34:27], &wdf_mask_data[25:18], wdf_mask_data[25:18], &wdf_mask_data[16:9], wdf_mask_data[16:9], &wdf_mask_data[7:0], wdf_mask_data[7:0]}; 

 

Replace lines 312 to 314 with: 

ecc_dm_error_r <= ( (~wdf_mask_r1[35] && (|wdf_mask_r1[34:27])) || (~wdf_mask_r1[26] && (|wdf_mask_r1[25:18])) || (~wdf_mask_r1[17] && (|wdf_mask_r1[16:9])) || (~wdf_mask_r1[8] && (|wdf_mask_r1[7:0]))) && phy_init_data_sel; 

VHDL - Edit phy_write.vhd 

Replace lines 328 to 331 with: 

wdf_mask_r <= (and_br(wdf_mask_data(34 downto 27)) & wdf_mask_data(34 downto 27) & and_br(wdf_mask_data(25 downto 18) & wdf_mask_data(25 downto 18) & and_br(wdf_mask_data(16 downto 9)) & wdf_mask_data(16 downto 9) & and_br(wdf_mask_data(7 downto 0)) & wdf_mask_data(7 downto 0)); 

Replace lines 366 to 370 with: 

ecc_dm_error_r <= ((not(wdf_mask_r1(35)) and (or_br(wdf_mask_r1(34 downto 27)))) or (not(wdf_mask_r1(26)) and (or_br(wdf_mask_r1(25 downto 18)))) or (not(wdf_mask_r1(17)) and (or_br(wdf_mask_r1(16 downto 9)))) or (not(wdf_mask_r1(8)) and (or_br(wdf_mask_r1(7 downto 0))))) and phy_init_data_sel; 

These issues are resolved in MIG 2.1.