We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Page Bookmarked

AR# 29505

9.2i EDK - PLBv46_PCI v1.00.a will not boot Linux when the PowerPC is running at 300 MHz clock and the plb bus is running at 100 MHz clock


PLBv46_PCI v1.00.a will not properly boot Linux when PowerPC is running at 300 MHz clock rate and the plb is running at 100 MHz clock. The failure is observed as corruption of data when Linux is scanning the PCI bus. This failure was found in a BSB ML410 system test that used the BSB Linux kernel. The root cause is that a configuration read transaction during PCI bus scan is performed as 4-byte reads. The source code specifies a single-word read, but the compiler breaks the word read into 4-byte reads, which occur in a very quick sequence. The bridge undergoes an error with this quick sequence and issues a RdErr on the bus with an interrupt. However, the kernel ignores the bus RdErr and interrupt. The kernel processes the corrupt data as if it were successful. When the CPU is running at 100 MHz, there is no corruption and Linux boots successfully, but when the CPU is running at 300 MHz, the second byte is corrupted.


This issue will be fixed in EDK 9.2i Service Pack 1 with the a new version of plbv46_pci v1.01.a core. The plbv46_pci v1.00.a, which was first released in EDK 9.2.0, will be deprecated in the EDK 9.2i Service Pack 1 release.

AR# 29505
Date 05/22/2014
Status Archive
Type General Article