If read operation is performed during RESET, the UNDERFLOW flag should be asserted. However, it does not do so in VHDL behavioral model simulation.
This issue has been addressed in FIFO Generator v4.3. We strongly recommend an upgrade to v4.3, but if this is not possible please use the following information:
This is a VHDL behavioral model issue only. The UNDERFLOW flag will function properly in the device.
To work around this, use a structural simulation model. To generate a structural simulation model, open Project Options in the CORE Generator GUI. Click on Generation tab and change simulation files to "Structural."