| AR# |
29515 |
| Part |
IP-MPMC |
| Last Modified |
2008-03-11 00:00:00.0 |
| Status |
Active |
| Keywords |
fail, ecc, error, ram, RAM |
Description
Keywords: fail, ecc, error, ram, RAM
When using the MPMC with ECC memory of widths less than 64-bits, a persistent single I/O failure will not be recoverable. How can this be resolved?
Solution
This limitation is caused by the narrower interfaces using the same ECC block for both edges of the DDR clock. Thus, a single I/O failing would cause a multiple-bit error as both data beats are used in the calculation.
There is currently no way to work around this behavior, but in cases other than two or more bit errors in a rising/falling data beat pair, the ECC will be robust.
This will be improved in a future version of the MPMC Core. NOTE: All memory widths will then require 8 ECC bits instead of the 4 bits currently used for 8-, 16- and 32-bit data memory interfaces.
The fix is currently planned for EDK 10.1i.
