When using the PLB and SDMA PIMs with a 1:2 clock ratio to the memory clock, timing failures occur at a faster required memory clock rate. My PIM should be running at half the memory rate. How do I resolve this issue?
The failing paths that occur in the PLB and SDMA PIMs running at half rate are caused by multicycle logic used to support 1:1 clocking. This issue will be fixed in a new version of the MPMC and PIMs, to be delivered in the EDK 9.2i Service Pack 2 tools.