UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 29522

LogiCORE RapidIO - Problem running Synplify flow with Serial RapidIO core

Description

When using Synplicity with the Serial RapidIO Core, some modifications are needed. See details for the specific device you are targeting.

Solution

Virtex-5

- You might receive the following error in the Synplify report:

"@E: CG161 :"S:\myproj\coregen\srio_v4_2_synplicity_v\example_design\gtp_wrapper_tile.v":427:9:427:19|parameter
PCS_COM_CFG cannot be found in module GTP_DUAL."

This error is a result of library files (unisim.v and unisim.vhd) delivered by Synplicity that are missing the PCS_COM_CFG parameter. Using Synplicity v9.0 or later should resolve this issue. Otherwise, see (Xilinx Answer 29248).

- Edit the UCF file as follows:

Change:

NET "rio_de_wrapper/mgt_reset_n" TIG;

To:

NET "rio_de_wrapper/lnk_reset_n" TIG;

Change:

NET "phy_4x_ser_clk/UCLK" TNM_NET = "UCLK";
NET "phy_4x_ser_clk/UCLK2" TNM_NET = "UCLK2";
NET "phy_4x_ser_clk/UCLK_DV4" TNM_NET = "UCLK_DV4";

To:

NET "phy_4x_ser_clk/UCLK_BUF" TNM_NET = "UCLK";
NET "phy_4x_ser_clk/UCLK2_BUF" TNM_NET = "UCLK2";
NET "phy_4x_ser_clk/UCLK_DV4_BUF" TNM_NET = "UCLK_DV4";

- In the same UCF file as above, add the following lines:

INST "rio_de_wrapper/phy_wrapper/rocketio_wrapper/gtp_wrapper/tile0_gtp_wrapper_i/gtp_dual_i" PCS_COM_CFG=28'h1680a0e;
INST "rio_de_wrapper/phy_wrapper/rocketio_wrapper/gtp_wrapper/tile1_gtp_wrapper_i/gtp_dual_i" PCS_COM_CFG=28'h1680a0e;


Virtex-4

- Edit the UCF file as follows:

Change:

NET "rio_de_wrapper/mgt_reset_n" TIG;

To:

NET "rio_de_wrapper/lnk_reset_n" TIG;

- When implementing the design example, you might receive the following MAP error:

"Mapping design into LUTs...
ERROR:MapLib:822 - RAMB16 symbol "user_top/initiator_user/initiator_bram/iram2"
has READ_WIDTH_A set to 18 and READ_WIDTH_B set to 18. This will result in
the disconnection of the following output pins:
DOA16, DOA17, DOA18, DOA19, DOA20, DOA21, DOA22, DOA23, DOA24, DOA25, DOA26,
DOA27, DOA28, DOA29, DOA30, DOA31, DOB16, DOB17, DOB18, DOB19, DOB20, DOB21,
DOB22, DOB23, DOB24, DOB25, DOB26, DOB27, DOB28, DOB29, DOB30, DOB31

These pins drive other logic in the design and will leave it sourceless.
Please change the value of READ_WIDTH_A/B or modify the design source and
"resynthesize."

The synthesis tool might not be mapping the ports properly on the initiator module of the design example. This issue should not affect the functionality of the Serial RapidIO Core.

Virtex-II Pro

No modification is needed for running Synplicity flow for Virtex-II Pro.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
40519 Serial RapidIO v5.6 - Release Notes and Known Issues for ISE Design Suite 13.1 N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
40519 Serial RapidIO v5.6 - Release Notes and Known Issues for ISE Design Suite 13.1 N/A N/A
AR# 29522
Date Created 10/28/2007
Last Updated 09/25/2012
Status Archive
Type Known Issues
IP
  • Serial RapidIO