We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 29533

9.2i Floorplan Editor - Multiple colors are displayed for Spartan-3A FPGA clock regions


Keywords: clock, region, color, boundary

In the Floorplan Editor, multiple colors are displayed for Spartan-3A FPGA clock regions. There are two clock regions in my design, the region shown in a solid coral green color between clock regions 0 and 2, and the other one in a solid purple color between clock regions 1 and 3. These two clock regions overlap each other, which is confusing. When is this going to be fixed?


This is a known issue and is fixed in ISE 10.1 release.
AR# 29533
Date 01/05/2009
Status Active
Type General Article
Page Bookmarked