The design crashes during placement phase 11.29:
Phase 10.8 (Checksum:38e5a00) REAL time: 5 mins 26 secs
Is this a known problem and is there a work-around?
A case has been seen where a Virtex-5 design crashes during placement phase 11.29. This problem was determined to be related to "register ordering" an algorithm that aligns registers based on bus names.
This problem will be fixed in ISE version 10.1. Meanwhile, this problem can be avoided by disabling the register ordering algorithm with the following environment variable:
Linux and Solaris
setenv XIL_PAR_NO_REG_ORDER 1
NOTE: The MAP switch "-r" can normally be used to disable register ordering, but has no effect on Virtex-5 designs at this time.
For general information about setting ISE environment variables, see (Xilinx Answer 11630).