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AR# 29545

9.2i EDK, PowerPC 405 - What are the valid multicycle or reset constraints on a PowerPC405 design using proc_sys_reset?

Description

What are the valid multicycle or reset constraints on a PowerPC 405 design using proc_sys_reset?

Solution

Generating an example design with Base System Builder is one way of determining valid timing exception constraints for processor systems. Currently, the only valid reset exceptions for a PowerPC 405 design are:

Net sys_rst_pin TIG; #External reset I/O which drives proc_sys_reset

NET "ppc_reset_bus_Chip_Reset_Req" TPTHRU = "RST_GRP";

NET "ppc_reset_bus_Core_Reset_Req" TPTHRU = "RST_GRP";

NET "ppc_reset_bus_System_Reset_Req" TPTHRU = "RST_GRP";

TIMESPEC "TS_RST1" = FROM CPUS THRU RST_GRP TO FFS TIG;

NOTE: The system using these constraints must have a similar reset structure to a Base System Builder design, including the use of the "proc_sys_reset" module.

AR# 29545
Date Created 10/28/2007
Last Updated 12/15/2012
Status Active
Type General Article