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AR# 29551

CPLD CoolRunner-II/XPLA3 - The functionality of a Latch in hardware is not as expected

Description

A Latch in CoolRunner-II/XPLA3 does not function correctly in hardware. However, the simulation appears correct.

Solution

The reason the LCDP does not function as expect is because the PRESET input does not have the priority documented in the Libraries Guide. According to the Libraries Guide, the PRE input should have the second priority after the ACLR input; however, it does not in hardware. The GATE input has a higher priority than the PRE input. This means that if PRE and GATE are both asserted, then GATE will influence the output of the latch; if D is low, then Q will also be low.

This is the expected behavior of the device. The Libraries Guide and simulation models will be updated to reflect this in a later version of the software.

To get the Latch to function with PRESET after CLR, a combinatorial latch can be created using the following code:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity LDCP_TEST is

Port ( PRESET : in std_logic;

CLR : in std_logic;

GATE : in std_logic;

D_in : in std_logic;

Q_out : out std_logic

);

end LDCP_TEST;

architecture Behavioral of LDCP_TEST is

signal int_Q: std_logic;

begin

Q_out <= int_Q;

int_Q <= not CLR and (PRESET or (int_Q and not GATE) or (int_Q and D_in) or (GATE and D_in));

end Behavioral;

AR# 29551
Date Created 10/28/2007
Last Updated 12/15/2012
Status Active
Type General Article