When I set the Design Flow in AccelDSP to be Hardware Co-sim, I have to turn OFF the Clock Enable Project Option.
In the 9.2.00 (build 967) release of AccelDSP, the Hardware Co-sim Flow (HW Co-sim) is selected, you must ensure that the Project Option "Clock Enable" is also set to "False." You can do this via the Project Option Menu, or via the command
SetProjectOption -clock_enable 0
If you do not set the Clock Enable Project Option to "False" or "0" from the command line, an incorrect netlist is built for the hardware, causing simulation failures.
This is fixed in the 9.2.01 release of AccelDSP.