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AR# 29559

Spartan-3E BPI configuration ROM data capture


When does the FPGA capture BPI ROM data? Is it on the rising or falling CCLK edge?


The FPGA-generated address outputs are clocked by the falling edge of CCLK.

The BPI ROM input data is captured on the rising CCLK edge by the FPGA.

This information is not clear in the Spartan-3 Generation User Guide. It will be updated in the next revision.

AR# 29559
Date Created 10/28/2007
Last Updated 12/15/2012
Status Active
Type General Article