AR #29564 - 10.1 EDK, MPMC v4.01.a - How can an MPMC2 design be upgraded to an MPMC v3.00a design and higher?

AR#	29564
Part	IP-MPMC
Last Modified	2008-08-18 00:00:00.0
Status	Active
Keywords	OPB, PLB, CDMAC, MPMC2, revup

Solution

Overview

MPMC versions starting with MPMC v3.00.a (released with EDK 9.2i), followed by MPMC v4.00.a (released with EDK 10.1) and later supersede MPMC2. The transition to MPMC v3 and later from MPMC2 will require the new instantiation of a new MPMC Core.

This Answer Record contains a short upgrade flow overview. The remainder of this solution outlines the changes and differences between MPMC2 and MPMC which an MPMC2 user should be aware of.

Upgrade Flow
Due to the significant bus architecture improvements starting in EDK 9.2i, it is generally easier to generate a new XPS system than try to rev up an older MPMC2 design.

The easiest method for creating a new EDK system is to use the XPS Base System Builder (BSB) wizard, which will create a new example system that can be modified. For MPMC, try to pick a development board that has a similar FPGA family and similar external memory type. BSB can be launched when creating a new XPS project.

Once a system is generated, configure the MPMC with a double-click or right-click->Configure IP on the MPMC instance in the System Assembly View. At this point, a GUI interface similar to the MPMC2 GUI should open. Then, reconfigure the MPMC PIMs and external memory settings as necessary to match the existing system (usually similar to the MPMC2 choices). If any settings are chosen that will change port widths to the external memory, be sure to correct the external port connections in the Port tab of the System Assembly View.

Next, configure the remaining peripherals of the new system. For more information on the remainder of the system peripherals, see the PLB v3.4 and OPB to PLBv4.6 System and Core Migration User Guide, included in the EDK 9.2i and later EDK installation.

IP Core Status and Support

Beginning with the release of EDK 9.2i in October 2007, MPMC2 is assigned an IP status of "available" while MPMC v3.00.a has the status "preferred." MPMC2 will begin the process of being phased out and deprecated as it is replaced by MPMC v3.00.a and later versions.

All new designs should begin using MPMC v4.00.a and later, which offers a number of enhancements over MPMC2. Existing MPMC2 designs should be migrated to MPMC3 whenever possible. For existing designs that must remain on MPMC2, support will continue for MPMC2 in accordance with the general OPB/PLBv34 phase out schedule described in (Xilinx Answer 29567).

Tool Flow Changes and Compatibility

MPMC Delivered as part of EDK
Beginning with EDK 9.2i, MPMC will no longer be delivered as a standalone download. It will be included in the EDK IP catalog and be part of the normal EDK installation.

MPMC IP Configuration GUI Integrated into XPS
Beginning with EDK 9.2i, the MPMC IP Configuration GUI is integrated within XPS. The MPMC GUI is no longer a standalone application. To access the MPMC GUI, right-click the MPMC Core in the XPS System Assembly View and select "Configure IP".

MPMC configuration fully specified by MHS file
The state or configuration of a given MPMC Core is fully specified within the MHS file. The MPMC configuration can be changed only by modifying the MHS file. Also, note that when the GUI writes out the MPMC parameter values to the MHS file, it omits parameter values that would be set to a default value. The GUI also omits MHS parameter values that are not active or applicable to the given configuration. These behaviors help keep the MHS MPMC instantiation simple.

Base System Builder (BSB) Support
BSB can build systems using MPMC when the DDR/DDR2 memory controller is enabled in the wizard.

Single Language / Mixed Language Simulation
Some parts of the MPMC HDL code (for example SDMA and PLBv46 PIMs) are written in VHDL, the rest is written in Verilog. Therefore, behavioral simulations of MPMC require a mixed mode (VHDL and Verilog) simulator, either NC-Sim or ModelSim. For single language simulation, a post synthesis or post PAR simulation is required.

MPMC2 to MPMC v4 "rev up" not supported
There is no tool provided to automatically rev up an MPMC2 design to an MPMC v3/v4 design.

Major Hardware Changes

PLBv34 and OPB PIMs replaced by PLBv46 PIM
The PLBv34 PIM and OPB PIM are not available in MPMC v3/v4. MPMC v3/v4 have a PLBv46 PIM. A PLBv46 to OPB bridge exists to connect to legacy OPB IP, but a PLBv34 to PLBv46 bridge does not exist. Consult the PLB Migration Guide for more information.

CDMAC PIM replaced by Soft DMA PIM
The CDMAC PIM is replaced by the Soft DMA PIM. The Soft DMA PIM has similar functionality as it processes LocalLink packets and uses a linked list of descriptors stored in memory to control DMA of the LocalLink packets into memory.

Internal Bridging feature removed
In MPMC2, transactions to a DPLB could be forwarded to OPB/PLBv34 master ports. This feature is not present in MPMC v3.00.a and later, and MPMC v3/v4 does not have any PLBv46 ports that will master a PLB bus. However, in EDK 9.2i, the bridging feature has been superseded by dual sets of PLBv46 ports in the new PPC405 v2.00.a wrapper.

The dedicated IPLB1/DPLB1 ports should be connected to the MPMC via individual PLB PIMs and will function as direct point-to-point connections. The PPC405 wrapper also has a secondary set of IPLB0/DPLB0 ports that can be connected to a shared PLBv46 bus with other processor peripherals. The multiported PPC405 wrapper architecture negates the need for a PLB bus PIM when no masters on the PLB need to master into memory.

Support for SDRAM (Single Data Rate DRAM memory)
MPMC v3.00.a and later support SDRAM memory up to 64 bits wide. ECC is not currently supported with SDRAM.

Control registers moved from DCR interface to PLBv46 interface
The ECC and Performance Monitor control registers have been moved from a DCR to a PLBv46 interface. The PLBv46 Baseline Slave interface used for the PLBv46 interface is a 32-bit singles-only slave described in: <EDK_Install>/doc/usenglish/sp026.pdf.

Virtex-II Pro devices supported only in MPMC v4
MPMC v3 does not support Virtex-II Pro.
MPMC v4 reintroduced Virtex-II Pro support.

Other Hardware Changes

NPI Interface Changes
The NPI interface has had some minor changes between MPMC2 and MPMC v3.00.a and later. The signal MPMC2_PIM_<PortNum>_RdFIFO_Data_Available was removed from the NPI interface.

NPI design parameters including base/high address and offset were also removed. In MPMC v3.00.a and later, there is no address decoding on NPI; the address flows directly to the memory device.

MPMC v3/v4 adds optional support for 32-bit data paths in the NPI interface. 32-bit NPI support permits less resource intensive interfacing to 32-bit devices. It also reduces MPMC BRAM/SRL FIFO utilization when used with 8- or 16-bit DDR memories and with 8-, 16-, or 32-bit SDRAM memories.

MPMC v3/v4 limited the NPI BRAM write FIFO size to 1024 bytes, relative to the MPMC2 maximum of 8KB, for timing and utilization reasons. User NPI applications which queue more than 1024 bytes before asserting NPI_AddrReq and allowing the MPMC to process the write to memory will be corrupted when migrating to MPMC v3 and later. See the MPMC v4.03.a and later data sheet for more detailed information on managing BRAM occupancy.

The 16-word burst transaction type was added to the NPI protocol. This filled in a gap between 8-word cache line and 32-word bursts supported by MPMC2.

The NPI bus type has been renamed from NPI to XIL_NPI. Modify any user NPI core MPDs to use the new label.

Please reference (Xilinx Answer 24912) - How do I create an NPI core and connect it to MPMC in EDK?

XCL enhancements
In MPMC2, the XCL PIM only supported XCL transaction types used by MicroBlaze (4/8-word read and 1-word write). In MPMC v3.00.a and later, the XCL PIM can be configured to support the full set of XCL transaction including burst writes, single word read, and 16-word read transactions.

Support for mixed FIFO configurations
MPMC v3/v4 allows for FIFO types to be mixed between SRL and block RAM FIFOs on a per port basis. FIFOs can also be selected to be read-only or write-only on a per port basis to reduce resource utilization.

Clock Ratio Auto-Detect for PLB/XCL PIMs
MPMC can automatically determine the clock ratio as 1:1 or 2:1 ration from memory clock rate to PIM clock rate. The clock ratio autodetect circuit is currently present in the PLB and XCL PIMs but not the SDMA PIM. The clock ratio autodetect means that the user does not have to set a clock ratio parameter for the PLB or XCL PIMs, previously needed in MPMC2.

Software Changes

DCR interfaces are replaced by memory mapped PLBv46 interface
MPMC v3.00.a and later control registers for ECC, Performance Monitors, and DMA are not software compatible with MPMC2 control registers.

Reference Designs

BSB Support
MPMC2 was shipped with a number of reference designs to help users get started building a system. These reference designs have been replaced by BSB support for MPMC v3/v4. For boards that BSB supports that have DDR/DDR2 interfaces, a system using MPMC can be easily generated, and serves as a starting point for user designs.

GSRD/GSRD2 Designs
MPMC v4 SDMA supports soft TEMAC on Spartan-3, Virtex-4, and Virtex-5 architectures. It also supports hard TEMAC cores on Virtex-4 and Virtex-5 devices with hard TEMAC blocks. This expands the number of architectures where MPMC v3/v4 can provide a Gigabit Ethernet solution compared to GSRD2 which supported only TEMAC of Virtex-4. The GSRD2 reference design from MPMC2 is now replaced by MPMC3 + SDMA + TEMAC designs, easily built with the BSB wizard. Additionally, future application notes will describe the performance and implementation considerations of high-performance, MPMC-based, networking designs.

Migration Considerations for Future MPMC Versions
(Xilinx Answer 29761) - How do I design a board to support future versions of MPMC and MIG?
(Xilinx Answer 30113) - 10.1 EDK, MPMC v4.00.a - What are the changes between MPMC v3 and MPMC v4?