LogiCORE FIFO Generator v4.2 - Programmable Full remains asserted after reset

AR#	29581	Search For Another Answer
Topic	IP-SysLogic-FIFO Generator
Last Updated	03/19/2008
Status	Active

Description

Keywords: CORE, Generator, IP, update, 9.2i, ip2_jm, fifogen, asynchronous, synchronous, common, clocks, memory, block RAM, BRAM, RAMB16, FIFO16, asynch, asymmetric, non-symmetric, first, word, fall, through, fwft, programmable, full, reset

When using common clock, Shift RAM configuration, I discover that Programmable Full flag does not behave properly.

When I have "full_reset_value" set to 1, and when RESET is asserted, all FULL flags including Programmable Full will be asserted to 1. When the RESET is deasserted, all FULL flags should deassert. However, Programmable Full flag remains asserted.

Solution

This issue has been addressed in FIFO Generator v4.3. We strongly recommend an upgrade to v4.3, but if this is not possible please use the following information:

This issue occurs because of an incorrect Verilog behavioral simulation model. The VHDL behavioral model behaves properly.

To work around this issue, use the structural simulation model. To generate a structural simulation model, open Project Options in the CORE Generator GUI. Click the Generation tab, and change simulation files to "Structural."