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AR# 29590

9.2 System Generator for DSP - After HDL netlist generation, why do I receive "ERROR XST:1370 Signal name my_out not found in design" if Verilog HDL is used as the output language?


My output language is Verilog and generation ran without errors. However, when I run synthesis, I receive the following errors in XST:

"ERROR:Xst:1370 - Line 18: Signal name my_out not found in design."

"ERROR:Parsers:11 - Encountered unrecognized constraint while parsing."

The errors reference some of my outputs from my System Generator design for which I have used the "Specify IOB location constraints" option.


This error can occur if you have a one-bit unsigned output driving a gateway out in your model and have specified the pin LOC constraint. In this case, the auto-generated XCF constraints file incorrectly uses the following syntax:

NET "my_out" LOC = "AF25";

The correct syntax should be:

NET "my_out[0]" LOC = "AF25";

To work around this, open the XCF constraint file and modify the one-bit output ports where necessary.

This will be addressed in a future System Generator for DSP release.

AR# 29590
Date 12/15/2012
Status Active
Type General Article
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