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AR# 29598

LogiCORE IP Floating Point Operator (FPO) - Release Notes and Known Issues

Description

This answer record contains the Release Notes and Known Issues list for the CORE Generator tool LogiCORE IP Floating Point Operator.

The following information is listed for each version of the core:

  • New Features
  • Bug Fixes
  • Known Issues

LogiCORE IP Floating Point Operator Lounge:
http://www.xilinx.com/products/ipcenter/FLOATING_PT.htm

Solution

General LogiCORE IP Floating Point Operator Issues

  • Support for the Virtex-6 FPGA lower power parts was added in this release, but this IP is not yet supported and cannot be generated from the CORE Generator tool.
    To work around this issue, you can set your project to target an equivalent Virtex-6 LXT device, which allows you to generate a place holder IP that can be regenerated when support for the Virtex-6 low-power parts are added in the 11.3.

LogiCORE IP Floating Point Operator v6.2

  • Initial release in Vivado 2012.4 design tools

Supported Devices (Vivado)

  • All 7 series (excluding Zynq-7000)

New Features

  • ISE design tools support removed
  • New operators:
    • exponential
    • fused multiply-add
    • accumulate

Resolved Issues

  • (Xilinx Answer 50927) - Why do I get error Failed to compile when trying to use Vivado Simulator 2012.2?
  • (Xilinx Answer 52199) - Why do I get a Synthesis CRITICALWARNING: [EDIF 20-96] when synthesizing the Floating Point Operators with Vivado Synthesis in 2012.2?

Known Issues (Vivado)

  • (Xilinx Answer 50909) - 2012.2 Vivado Simulator - Why do I receive errors or data mismatches when I attempt to simulate my IP in Vivado Simulator using the behavioral simulation flow?

LogiCORE IP Floating Point Operator v6.1

  • Initial release in ISE 14.2 and Vivado 2012.2 design tools

Supported Devices (ISE)

  • All 7 series
  • All Virtex-6
  • All Spartan-6

Supported Devices (Vivado)

  • All 7 series (excluding Zynq-7000)

New Features

  • New operators:
    • absolute value
    • natural algorithm

Resolved Issues

  • N/A

Known Issues (ISE)

  • N/A

Known Issues (Vivado)

  • (Xilinx Answer 50927) - Why do I get error Failed to compile when trying to use Vivado Simulator 2012.2?
  • (Xilinx Answer 50909) - 2012.2 Vivado Simulator - Why do I receive errors or data mismatches when I attempt to simulate my IP in Vivado Simulator using the behavioral simulation flow?
  • (Xilinx Answer 52199) - Why do I get a Synthesis CRITICALWARNING: [EDIF 20-96] when synthesizing the Floating Point Operators with Vivado Synthesis in 2012.2?


LogiCORE IP Floating Point Operator v6.0

  • Initial release in ISE Design Suite 13.2
Supported Devices
*To access these devices in the ISE Design Suite, contact your Xilinx FAE.
  • Zynq-7000*
  • Virtex-7
  • Virtex-7 XT (7vx485t)
  • Virtex-7 -2L
  • Kintex-7
  • Kintex-7 -2L
  • Artix-7*
  • Virtex-6 XC CXT/LXT/SXT/HXT
  • Virtex-6 XQ LXT/SXT
  • Virtex-6 -1L XC LXT/SXT
  • Virtex-6 -1L XQ LXT/SXT
  • Spartan-6 XC LX/LXT
  • Spartan-6 XA LX/LXT
  • Spartan-6 XQ LX/LXT
  • Spartan-6 -1L XC LX
  • Spartan-6 -1L XQ LX
New Features
  • ISE 13.2 design tools support
  • AXI4-Stream interfaces
  • New operators:
    • reciprocal: 1/x
    • reciprocal square root: 1/sqrt(x)
  • Bit-accurate C model
Bug Fixes
  • N/A
Known Issues (ISE)
  • N/A

Known Issues (Vivado)

  • (Xilinx Answer 47334) - Why do I see unexpected results when using a VHDL post-synthesis simulation model?

LogiCORE IP Floating Point Operator v5.0
  • Initial release in the ISE Design Suite 11.2
New Features
  • ISE 11.2 design tools support
  • Virtex-6 and Spartan-6 device support
Bug Fixes
  • CR470172 Support for -u map option for all operators (for use with the PlanAhead tool)
    • All operators should now go through map with -u option specified.
    • (Xilinx Answer 30806) - Why does ISE 10.1 MAP fail, when the map -u options is used with the PlanAhead block-based implementation capability?
  • CR470376 SCLR/CE priority clarification in data sheet
    • The behavior that SCLR overrides CE is now also mentioned in the description of the SCLR port in Table 2.
  • CR487995 Data sheet should clearly state that SCLR does not clear datapath
    • The behavior that SCLR only resets control path is now explicitly mentioned in the description of the SCLR port in Table 2.
  • CR470377 Data sheet documents HDL generics - this interface is no longer supported
    • The only supported customer interface for core generation is through CORE Generator interface. The description of the HDL generics has been removed from the data sheet.
  • CR477962 Data sheet should be enhanced with numerical examples
  • An example C-code program has been provided in the data sheet to enable customers to replicate core behavior at single precision with a desktop computer. This assumes that denormalized numbers are not used. This code can be used to generate hexadecimal values for comparison with an HDL simulation of the core.
  • CR483358 SCLR should be greyed out in interface when not applicable
    • SCLR and CE are no longer available when latency is set to zero, as there is no clock port.
  • CR481413 Data sheet has incorrect equation (page 2, bounds for fractional part)
    • The lower bound for the fractional part (with hidden bit) is now correctly specified as 1. That is: 1 <= b0.b1...bp-1 < 2.
Known Issues LogiCORE IP Floating Point Operator v4.0
  • Initial release in ISE 10.1 IP Update 1
New Features
  • Spartan-3A DSP support
  • Increased speed of fabric and DSP48E based double precision adders on Virtex-5 devices
  • Latency and resources reductions for Virtex-5 single and double precision multipliers
  • Increased range of multiplier usage options for Virtex-5 double precision multiplier
  • Reduced latency compare and round operations
Bug Fixes
  • CR443418: Behavior of denormalized numbers - Data sheet modified to explain in more detail how denormalized numbers are handled by the core.
  • CR442822: Single precision adder failing timing on Virtex-5 - Enhancements in XST's block RAM inference support resulted in a fabric 6-input look-up-table being converted to block RAM. The associated routing to and from block RAM reduced operational frequency. The threshold at which BRAMs are used on Virtex-5 has been increased in 10.1, and so they are on longer inferred within this core. This XST fix will apply to v3.0 and v4.0 of the core.
  • CR441538: NC-Sim warning - This simulation model has been modified in v4.0 to remove this warning. - Note that this warning will still be generated by v3.0 of the core.
  • CR433981: Incorrect GUI pop-up message on page 3 - Fixed in version 4.0. - Latency field popup messages for when "Use Maximum Latency" ticked and unticked were swapped. These have been fixed.
  • CR468257: MAP fails when -u option is used with environment variable XIL_MAP_NOCLIP_ON_ALL_SIGS_U set to 1 - Required by PlanAhead block-based implementation capability - Partially fixed in version 4.0. All add/subtract, DSP48/E/A based multiply, compare and float-to-float conversion operations can now be mapped in this way.
Known Issues
LogiCORE IP Floating Point Operator v3.0
  • Initial release in ISE 8.2i IP Update 2 software
New Features
  • Virtex-5 device support, including:
    • New option allows adder to make use of DSP48E in Virtex-5 or DSP48 in Virtex-4
    • Multiplier now supports DSP48E
    • Option to construct single precision multiplier from 1 DSP48E + logic
    • Low latency adder architecture supported on Virtex-5 implementations
  • Support for higher levels of pipelining in adder and multiplier for increased speed
  • Improved size and speed of square root
  • Conversion operations between floating-point types added
  • Resource and speed estimation provided in customization GUI
  • Support removed for Virtex and Spartan-II devices. Please use the v2.0 core if targeting these architectures
Bug Fixes
  • CR 226251: Compare should have a result of 1-bit rather than use bit 0 of larger output
Known Issues
  • (Xilinx Answer 24039) - Why do I not see a resource estimation graph for my Floating Point operator function?
  • (Xilinx Answer 25438) - When I generate in ISE 9.2i, why am I unable to ;reach the 410 MHz performance listed for the Floating Point Adder in the data sheet?
  • (Xilinx Answer 29597) - When I generate in ISE 9.2i, why are the simulation results of my double precision floating point multiplier incorrect?

LogiCORE IP Floating Point Operator v2.0
  • Initial release in ISE 8.1i IP Update 1
New Features
  • Support for conversion to and from fixed-point
  • Greater choice of word length
  • User-specifiable latency
  • Level of hardware reuse for divide and square-root can be specified
  • Support for clock enable
Bug Fixes
  • CR 213669: Data sheet does not contain timing information
  • CR 214410: GUI must have dynamic format diagram
Known Issues
  • N/A

LogiCORE IP Floating Point Operator v1.0 r1
  • Initial release in ISE 7.1i IP Update 2
New Features
  • N/A
Bug Fixes
  • CR 209982: Data sheet modified to explain how a Verilog simulation model can be generated for the core.
Known Issues
  • N/A

LogiCORE IP Floating Point Operator v1.0
  • Initial release in ISE 7.1i IP Update 1
New Features
  • First release
  • IEEE-754-compliant floating-point operators with only minor documented deviations
  • Can be configured for high-speed operation with an instruction issued on every clock cycle
  • Supports add/subtract, multiply, divide and square-root operations, with a range of standard and nonstandard sizes, including single and double precision
  • Support for Virtex-4 DSP48 feature
  • Includes multi-cycle divide and compare operations for single precision
  • VHDL behavioral model
  • Core can be generated directly from a VHDL instantiation with XST transparently calling CORE Generator
Bug Fixes
  • N/A
Known Issues
  • N/A

Linked Answer Records

Associated Answer Records

AR# 29598
Date Created 10/28/2007
Last Updated 10/09/2013
Status Active
Type Release Notes
IP
  • Floating-Point Operators