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AR# 29630

Virtex-5 Embedded Tri-mode Ethernet MAC Wrapper v1.3 and earlier - SGMII Auto Negotiation never completes

Description

Keywords: Virtex-5, TEMAC, tri-speed, AN, PHY, buffer, error, overflow

When the EMAC wrappers are generated for SGMII with the fabric elastic buffer, Auto Negotiation sometimes does not complete with the current reset logic. The fabric elastic buffer is used by default when the wrappers are generated for Tri-speed operation.

During Auto Negotiation, no clock correction sequences are sent so it is expected that a buffer error could occur. The TEMAC is designed to ignore errors in the incoming data when a buffer error is seen, to allow time for the buffer to be reset, and then resume Auto Negotiation. The current wrapper files reset both the over-/underflowing fabric elastic buffer and the GTP RX buffer. Resetting both buffers causes errors to reach the TEMAC after it has already resumed Auto Negotiation. The reset to GTP RX buffer is not needed; it will not over-/underflow as the rx recovered clock is used to clock both sides of the buffer. The fix for this issue is only to reset the fabric buffer.

This is not an issue for 1000BASE-X (which does not use the fabric buffer) or SGMII, when the fabric buffer is not selected.

Solution

Below show the code changes needed to change RXRESET_0_REC so that it will not be issued when there is a fabric buffer error. If both GTPs are used, then the logic for RXRESET_1_REC will need to be changed as well.

To fix this for VHDL in example_design/physical/gtp_dual_1000X.vhd change:

rxrstreclock0 : process(RXRECCLK_0_BUFR, RXRESET_0)
begin
if RXRESET_0 = '1' then
RXRESET_0_REG <= '1';
RXRESET_0_REC <= '1';
elsif RXRECCLK_0_BUFR'event and RXRECCLK_0_BUFR = '1' then
RXRESET_0_REG <= '0';
RXRESET_0_REC <= RXRESET_0_REG;
end if;
end process rxrstreclock0;

To:

rxrstreclock0 : process(RXRECCLK_0_BUFR, PMARESET)
begin
if PMARESET= '1' then
RXRESET_0_REG <= '1';
RXRESET_0_REC <= '1';
elsif RXRECCLK_0_BUFR'event and RXRECCLK_0_BUFR = '1' then
RXRESET_0_REG <= '0';
RXRESET_0_REC <= RXRESET_0_REG;
end if;
end process rxrstreclock0;

To fix this for Verilog in example_design/physical/gtp_dual_1000X.v change:

always @(posedge RXRECCLK_0_BUFR or posedge RXRESET_0)
begin
if (RXRESET_0 == 1'b1)
begin
RXRESET_0_REG <=1'b1;
RXRESET_0_REC <=1'b1;
end
else
begin
RXRESET_0_REG <= 1'b0;
RXRESET_0_REC <= RXRESET_0_REG;
end
end

To:

always @(posedge RXRECCLK_0_BUFR or posedge PMARESET)
begin
if (PMARESET == 1'b1)
begin
RXRESET_0_REG <=1'b1;
RXRESET_0_REC <=1'b1;
end
else
begin
RXRESET_0_REG <= 1'b0;
RXRESET_0_REC <= RXRESET_0_REG;
end
end




AR# 29630
Date Created 10/28/2007
Last Updated 10/22/2007
Status Active
Type General Article