If I add my System Generator PLB PCORE to an EDK project, it fails with the following error if there are any peripherals on the bus which are 64-bit or 128-bit peripherals:
ERROR:MDT - INST:<pcore_instance_name> PORT:plb_wrdbus
CONNECTOR:mb_plb_PLB_wrDBus - <path_to_sysgen_pcore>\<pcore_name>.mpd line 56 - calculated index is out of signal VEC range of [0:63]
When generating a PLB PCORE from a System Generator model, only the 32-bit PLB bus is currently supported. This requires that all the peripherals on the bus must also be set up in 32-bit mode where applicable. If any peripherals in the EDK project require a 64- or 128-bit PLB bus, a System Generator PLB PCORE will not be compatible.
9.2.01 System Generator for DSP PCORE supports only either FSL or 32-bit PLB interfaces.
For a complete list of 9.2.01 Release Notes and Known Issues see (Xilinx Answer 29632)