How do Xilinx Endpoints for PCI Express handle Vendor Defined Messages?
How should the user application handle Vendor Defined Messages when passed from the PCIe Core?
Many times, the switch or root complex communicating with the Xilinx endpoint core will transmit Vendor Defined Messages to the endpoint. The reason for these messages varies, and users should consult the documentation of the transmitting device to find the meaning of the Vendor Defined Message.
The Xilinx core passes all received Vendor Defined Messages to the user application. The user application must drain Vendor Defined Messages from the core to free up receive buffer space. The user application can discard these packets if they are not needed.
If the user application does not drain Vendor Defined Messages, the cores posted receive buffer might fill. Typical system behavior results in the root throttling the link due to lack of flow control credits advertised by the endpoint.
NOTE: This Answer Record applies to all PCIe Endpoint cores from Xilinx.
10/29/2007 - Initial Release
10/12/2009 - Added "NOTE" indicating AR applies to all endpoint cores