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AR# 29685

LogiCORE RapidIO v4.2 - Default "simulate_mti.do" simulation script is missing continuation character and produces an error

Description

The LogiCORE Serial RapidIO simulation script (simulate_mti.do) provided with the core produces an error when attempting to simulate the example design in Modelsim.

Solution

This issue results from a missing continuation character on line 121 of the .do file.

Add "\" at the end of this line.

Below is how the code should read to successfully simulate the example design:

#-----------------------------------------------------------------------------

# Core Simulation Netlists

#-----------------------------------------------------------------------------

vcom -work work -93 \ <-----------

../../srio_phy_v4_2.vhd \

../../rio_log_io_v4_2.vhd

Note: This issue is present only when generating the core with VHDL as the Design Entry specification within Core generator project options. This issue is not present when generating the core with Verilog selected in the Design Entry field.

AR# 29685
Date Created 11/03/2007
Last Updated 12/15/2012
Status Active
Type General Article