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AR# 29691

9.2i EDK, MPMC v3.00a - ERROR: IO Clock Net "delayed_dqs<0>" cannot possibly be routed to component "u_iserdes_dq"

Description

The following error occurs when I try to implement a Virtex-5 DDR MPMC design:

"IO Clock Net "i_mpmc2/mpmc2_core_0/gen_v5_phy_top.gen_ddr_phy.mpmc2_phy_if_0/u_phy_io/delayed_dqs<3>"

cannot possibly be routed to component "i_mpmc2/mpmc2_core_0/gen_v5_phy_top.gen_ddr_phy.mpmc2_phy_if_0/u_phy_io/gen_dq[26].u_iob_dq/u_iserdes_dq" (placed in clock region "CLOCKREGION_X0Y0"),

since it is too far away from source BUFIO

"i_mpmc2/mpmc2_core_0/gen_v5_phy_top.gen_ddr_phy.mpmc2_phy_if_0/u_phy_io/gen_dqs[3].gen_phy_dqs_iob_gate.u_iob_dqs/u_bufio_dqs"

(placed in clock region "CLOCKREGION_X0Y1").

The situation may be caused by user constraints, or the complexity of the design. Constraining the components related to the regional clock properly may guide the tool to find a solution."

How do I resolve this issue?

Solution

Virtex-5 designs interfacing to DDR external memories using the MIG PHY will experience this issue if MIG placement constraints are not imported to the EDK "system.ucf". The "convert_ucf.pl" script will now rename the Virtex-5 DDR constraints, and the MPMC data sheet now details the flow to import the MIG UCF.

The first version containing this fix is EDK 9.2i, Service Pack 1.

AR# 29691
Date Created 11/03/2007
Last Updated 02/25/2013
Status Active
Type General Article