We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 29698

9.2i EDK, MPMC v3.00a - Data corruption occurs on memory writes when using read-only PIM on port 0, and different write FIFO pipeline settings


Incorrect data is being written into external memory. My design contains a read-only PIM on port 0, including the IXCL or IPLB subtypes, and different C_PI<Port_Num>_WR_FIFO_MEM_PIPELINE pipeline values between port 0 and other ports. How do I resolve this issue?


The easiest way to work around this issue is to reconfigure the MPMC core and its bus connections so that a PIM that performs both reads and writes resides on port 0 of the MPMC. An example would be the data-side memory connection of a processor. Alternatively, ensure that all ports have the same C_PI<Port_Num>_WR_FIFO_MEM_PIPELINE value. 


This issue is currently planned to be fixed in EDK 10.1i.

AR# 29698
Date Created 11/03/2007
Last Updated 05/22/2014
Status Archive
Type General Article