Overview

Pack:679 and Pack:2811 errors are general purpose errors that handle a wide variety of error conditions that might occur if the packer is unable to resolve hard constraints. The constraints involved might be packing constraints or location constraints since, in either case, logic elements are constrained to the same component.

Example of Pack:679 message

ERROR:Pack:679 - Unable to obey design constraints (LOC =SLICE_X0Y0) which require the combination of the following symbols into a single slice component:
FLOP symbol ...
FLOP symbol ...
The clock signals don't agree. Please correct the design constraints accordingly.

Understanding the three sections of the message

• The first section of the error message lists the hard MAP constraint that the packer is unable to resolve. In this example two FLOP instances share the LOC constraint "LOC = SLICE_X0Y0".
• The second section of the message lists all of the constrained symbols involved. In this example, two FLOPs are listed.
• The third and last section describes the reason that the packer cannot resolve the constraints. In this example, the constrained Flops do not share the same clock signal. It is not possible to configure two FLOPs in the same slice with different clock signals due to limitations in the hardware.

Example of Pack:2811 message

ERROR:Pack:2811 - Directed packing was unable to obey the user design constraints (LOC=A13) which requires the combination of the symbols listed below to be packed into a single IBUF component.

The directed pack was not possible because: There is more than one pad symbol.
The symbols involved are:
BUF symbol "BPI_CS_N_I_ibuf(0)" (Output Signal = BPI_CS_N_I_int(0))
PAD symbol "BPI_CS_N_I(0)" (Pad Signal = BPI_CS_N_I(0))
PAD symbol "BPI_CS_N_I(1)" (Pad Signal = BPI_CS_N_I(1))

Understanding the three sections of the message

• The first section of the error message lists the hard MAP constraint that the packer is unable to resolve. In this example two PAD instances and a BUF instance share the LOC constraint "LOC = A13".
• The second section of the message describes the reason for the failure: "There is more than one pad symbol".
• The third and last section lists all of the symbols involved.

Debug steps

In these simple cases, it is easy to identify the root cause of the pack failure. Other cases can be more difficult to understand but can be debugged by examining the details of the logic involved and the error reported. All pack errors involve a resource limitation in the component involved (Slices, IOBs, etc.). This limitation is either a BEL (Basic Element of Logic) based limitation or a connectivity restriction as in the example above. BEL conflicts are easy to debug. For example, it is not hard to understand why a Pack:679 error would occur if three LUTs are constrained to a single Virtex-4 Slice that contains only two LUT BELs. Connectivity restrictions can be harder to understand since they require a more detailed understanding of the resources available in the component and the logic that is targeted to the component. The following steps can be used to debug the root cause of the error:

• Identify the constraint causing a problem from section one.
• Examine the symbols involved.
• Analyze the error summary to identify the reason for the conflict.
• Examine the logical design and compare to the information available in the error message.
• If the nature of the conflict is still unclear, attempt to configure the circuit in the Logic Block Editor in FPGA Editor. This can be useful to identify a resource conflict that is not otherwise apparent. Sometimes, just examining the connectivity resources available in LBE is enough to identify the source of the problem.
• Search existing Answer Records for a known problem related to a similar pack error. When evaluating the applicability of particular Answer Records, compare the details to determine whether the Answer Record is a good match. Ensure that the same component type and conflict summary (section 3) is involved.
• If the logical design can be successfully implemented using LBE and no known problems can be found to explain the failure, it is reasonable to assume that a new MAP pack bug has been identified and a WebCase should be opened to report the problem to Xilinx.

Current known causes of Pack:679 errors
(Xilinx Answer 6968) - Floorplanner does not check for clock conflicts for Slice FFs
(Xilinx Answer 6968) - Floorplanner allows standard I/O components to be improperly constrained to clock IOBs
(Xilinx Answer 18889) - MAP incorrectly optimizes MUXCYs and XORCYs to LUTs causing a conflict
(Xilinx Answer 8926) - Two signals accidently constrained to the same pad
(Xilinx Answer 23694) - Failed inverter push blocks a legal slice pack