| AR# |
29737 |
| Part |
IP-MPMC |
| Last Modified |
2007-11-17 00:00:00.0 |
| Status |
Active |
| Keywords |
MPMC3, speed, frequency, maximum, designs, support, memory, DDR, DDR2, SDRAM |
Description
Keywords: MPMC3, speed, frequency, maximum, designs, support, memory, DDR, DDR2, SDRAM
With the release of the MPMC memory controller supported by the EDK 9.2i design tools, what memory solutions are supported and at what frequencies?
Solution
DDR2, DDR, and SDRAM memory devices are supported by the EDK MPMC3 memory controller.
Target FPGA--Target fMAX
Device---------Range (MHz)
-----------------------------
Spartan-3 -4.....125-133
Spartan-3 -5.....133-150
Virtex-4 -10......160-180
Virtex-4 -11......180-200
Virtex-4 -12......200-220
Virtex-5 -1........155-180
Virtex-5 -2........175-200
Virtex-5 -3........200-220
NOTE: These are currently measured system frequencies. Higher frequencies than those quoted can be reached with additional floorplanning. Due to the default usage of block RAMs for data FIFOs, it is often worthwhile to locate block RAM locations. Another floorplanning tip is to create an area group of the PHY interface module and range it near the memory I/O locations.
This information will be included in the MPMC data sheet starting with EDK 9.2i, Service Pack 2.
