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AR# 29754

9.2i sp3 Map - ERROR:PhysDesignRules:1701 - Unsupported configuration for PLL_ADV comp u_analog_L015/u_PG18A1/U2_pll312m/PLL_ADV_INST

Description

The customer connects DCM_ADV to PLL_ADV. The error appears when the PLL_ADV CLKFBIN input pin being driven by the CLKFBDCM pin. See below:

ERROR:PhysDesignRules:1701 - Unsupported configuration for PLL_ADV comp u_analog_L015/u_PG18A1/U2_pll312m/PLL_ADV_INST.

The PLL_ADV CLKFBIN input pin is driven by the CLKFBDCM pin. This connectivity requires that the COMPENSATION

attribute to be set PLL2DCM and it is set to SYSTEM_SYNCHRONOUS. The connectivity for CLKFBIN or the COMPENSATION

attribute must be changed.

Solution

The cause of this issue is that the PLL_ADV CLKFBIN input pin is driven by the CLKFBDCM pin. Use CLKFBOUT pin to drive CLKFBDCM pin. For more information, see the Virtex-5 User Guide, "DCM Driving PLL":

http://www.xilinx.com/support/documentation/virtex-5_user_guides.htm

AR# 29754
Date Created 11/14/2007
Last Updated 12/15/2012
Status Active
Type General Article