The customer connects DCM_ADV to PLL_ADV. The error appears when the PLL_ADV CLKFBIN input pin being driven by the CLKFBDCM pin. See below:
ERROR:PhysDesignRules:1701 - Unsupported configuration for PLL_ADV comp u_analog_L015/u_PG18A1/U2_pll312m/PLL_ADV_INST.
The PLL_ADV CLKFBIN input pin is driven by the CLKFBDCM pin. This connectivity requires that the COMPENSATION
attribute to be set PLL2DCM and it is set to SYSTEM_SYNCHRONOUS. The connectivity for CLKFBIN or the COMPENSATION
attribute must be changed.
The cause of this issue is that the PLL_ADV CLKFBIN input pin is driven by the CLKFBDCM pin. Use CLKFBOUT pin to drive CLKFBDCM pin. For more information, see the Virtex-5 User Guide, "DCM Driving PLL":