We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 29764

9.2 ChipScope Pro: The example HDL template is generated incorrectly for the ATC2 core


When generating the ATC2 core with a signal bank count is set to 64 the HDL template is generated incorrectly with only a 32 signal bank count.


The other generated files generated [<core_name>.ncf, <core_name>.cdc, <core_name>.arg, <core_name>.edn] are correct. To HDL template it will need to be modified to add the extra channels. This issue will be resolved in the Chipscope Pro 10.1 release.

AR# 29764
Date Created 05/15/2008
Last Updated 05/22/2014
Status Archive
Type General Article