We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 29772

9.2i EDK - Constraint written by tcl file for OPB_CAN_v1_00_a is not analyzed by Timing Analyzer


In the OPB_CAN_v1_00_a, if the opb_clk and can_clk are connected to the same clock source, one of the constraints written out by the TCL file applies a "TIG FROM sysclk TO sysclk", which voids the entire period constraint. This causes the signal to not be analyzed in Timing Analyzer.


The OPB_CAN_v1_00_a core does not support the use of a single clock source for both the opb_clk and the can_clk.  


To work around this issue, you will need to use two different clocks for the opb_clk and the can_clk.

AR# 29772
Date Created 07/25/2008
Last Updated 05/22/2014
Status Archive
Type General Article