The Virtex-5 DDR2 SDRAM design for MIG 2.0 issues an incorrect RAS command during the following sequence:
1. Refresh counter indicates a refresh is required.
2. Controller issues PRECHARGE ALL BANKS in preparation for refresh.
3. Controller issues AUTO REFRESH.
4. Controller reopens (issues ACTIVATE) the previous row accessed. This occurs regardless of whether there is a read/write pending in the Address/Command FIFO for this bank.
5. Controller receives a request to access a new row in the same bank and issues ACTIVATE the new row, without precharging the old row or waiting tRC.
This issue appearsin both simulation and hardware.
Changes were required to the controller state machine to resolve this issue. The ctrl.v/.vhd has been updated to issue ACTIVATE only if there are pending commands after completion of AUTO REFRESH.
The updated file can be downloaded from the following location:
1. Replace the ctrl.v/vhd, generated with the MIG 2.0 output, with the above ctrl.v/.vhd file.
2. Re-run the design.
This issue is resolved in MIG 2.1.