AR #29784 - 9.2i EDK - In MicroBlaze v7.00.a, erroneous exceptions following an interrupt can occur
9.2i EDK - In MicroBlaze v7.00.a, erroneous exceptions following an interrupt can occur
| AR# | 29784 |
| Part | IP-Processor |
| Last Modified | 2007-12-04 00:00:00.0 |
| Status | Active |
| Keywords | interrupt, IRQ, exception, pre, fetch, MB, handle, handling, routine |
Description
Keywords: interrupt, IRQ, exception, pre, fetch, MB, handle, handling, routine
When an interrupt is being handled by MicroBlaze, any subsequent instructions already fetched should be ignored and just pass through the processor pipeline without any effect. However, an exception occurring for any of these instructions is not ignored, erroneously causing it to be handled instead of the interrupt. The only affected exceptions are illegal opcode, instruction bus error, and instruction memory management exceptions.
A situation when this can occur is when the fetched instructions are illegal (which can be the case if prefetching past the last instruction in the code section), the interrupt occurs for the last instruction in the code section, and illegal opcode exceptions are enabled.
The problem is more likely to occur in systems where exceptions are more frequent; for example, Linux systems with the MMU enabled.
Solution
A patch is available at:ftp://ftp.xilinx.com/pub/swhelp/ise9_updates/edk_92i_mb_v700a_patch.zip
1 - Go into the $Xilinx_EDK\hw\XilinxProcessorIPLib\pcores directory
2 - Rename the microblaze_v7_00_a directory to microblaze_v7_00_a_old
3 - Unzip the file into the $Xilinx_EDK directory
This problem will be resolved in MicroBlaze version 7.00.b.
This problem has been fixed in the latest EDK 9.2i Service Pack, available at:
http://www.xilinx.com/xlnx/xil_sw_updates_home.jsp
The first service pack containing the fix is EDK 9.2i Service Pack 2.