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AR# 29829

9.2i EDK, MPMC v3.00a - HDLCompilers:191 Indices in part-select of vector reg 'Col_Cnt' are reversed

Description

Keywords: row, address, width, 11, indices, part-select, vector, Col_Cnt, illegal, HDLCompilers, 185, 191

In order to support 8MB SDRAM devices, the parameter C_NUM_MEM_PARTS_ROW_BITS has to be set to 11, according to the mpmc core data sheet. EDK (V9.2 SP1) then automatically sets C_MEM_ADDR_WIDTH to the same value.

However, XST synthesis aborts with an array index error in a Verilog source file of the Xilinx mpmc core (see also error messages below). The corresponding source code line is:

assign Col_Addr_Full = {Col_Cnt[C_MEM_ADDR_WIDTH-2:10], Ctrl_AP_Precharge_Addr10, Col_Cnt[9:0]};

-------------------------------
This is from the Error Message
------------------------------
HDLCompilers:191 - "C:\Programme\EDK92\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_a/hdl/verilog/mpmc_addr_path.v" line 543
Indices in part-select of vector reg 'Col_Cnt' are reversed
ERROR:HDLCompilers:185 - "C:\Programme\EDK92\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_a/hdl/verilog/mpmc_addr_path.v" line 543
Illegal right hand side of continuous assign
ERROR:MDT - Aborting XST flow execution!

Solution

This issue is fixed in EDK 9.2i Service Pack 2 and later versions.

To work around this issue, please modify the "mpmc_addr_path.v" as below.

Replace:
assign Col_Addr_Full = {Col_Cnt[C_MEM_ADDR_WIDTH-2:10], Ctrl_AP_Precharge_Addr10, Col_Cnt[9:0]};

With:
generate
if (C_MEM_ADDR_WIDTH == 11) begin : col_addr_11
assign Col_Addr_Full = {Ctrl_AP_Precharge_Addr10, Col_Cnt[9:0]};
end
else begin : col_addr
assign Col_Addr_Full = {Col_Cnt[C_MEM_ADDR_WIDTH-2:10], Ctrl_AP_Precharge_Addr10, Col_Cnt[9:0]};
end
endgenerate
AR# 29829
Date Created 11/19/2007
Last Updated 12/11/2007
Status Active
Type General Article