My design does not ever assert the ODT signal, causing calibration to fail or produce data errors. How do I resolve this issue?
To manually fix this issue:
1) Copy the %Xilinx_EDK%\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_a directory to the local project pcores directory
2) Add the following line to the new directories pcores\mpmc_v3_00_a\hdl\verilog\mpmc.v file, line 2585 and save:
assign DDR2_ODT = MEM_ODT;
3) In XPS, choose Project->Rescan User Repositories
4) Rebuild design
The first version containing this fix is mpmc_v3_00_b, which is contained in Xilinx EDK 9.2, Service Pack 2.