We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 29844

9.2i EDK, MPMC v3.00a - ODT not connected for DDR2 designs


My design does not ever assert the ODT signal, causing calibration to fail or produce data errors. How do I resolve this issue?


To manually fix this issue: 

1) Copy the %Xilinx_EDK%\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_a directory to the local project pcores directory 

2) Add the following line to the new directories pcores\mpmc_v3_00_a\hdl\verilog\mpmc.v file, line 2585 and save: 

assign DDR2_ODT = MEM_ODT; 

3) In XPS, choose Project->Rescan User Repositories 

4) Rebuild design 


The first version containing this fix is mpmc_v3_00_b, which is contained in Xilinx EDK 9.2, Service Pack 2.

AR# 29844
Date 05/22/2014
Status Archive
Type General Article
Page Bookmarked