We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 29845

Spartan-II, Spartan-IIE, Virtex, Virtex-E - CLKDV output of the DLL does not toggle


There is a known issue where the DLL might not output a valid CLKDV clock even though CLK0 toggles and LOCKED goes High.

This intermittent issue is seen as a flat-line (constant high or constant low) of CLKDV, but the LOCKED output still goes High. The other outputs of the DLL (CLK0, CLK90, CLK180, CLK270) are not affected.


Devices Affected:

Spartan-IIE Automotive
Virtex Q ProVirtex-E
Virtex-E M Grade
Virtex-E Q Pro

Failure Mechanism:

The DLL has a separate set/reset enable logic circuit for the CLKDV output. There exists a race condition between the phase select logic and the input clocks to a mux that can lead to low pulses. The occurrence of these pulses is dependent on clock period, process variation, voltage, and temperature. It has been shown that narrow pulses can prevent any further transitions on CLKDV (i.e., ClKDV stops flat).

The failure is rarely seen and does not occur above a frequency of 60 MHz. When it does exhibit itself, it occurs within a very small window of time. The width of the pulse that can cause such a failure is extremely narrow, so small changes in clock period (frequency), temperature, or voltage moves the failing DLL out of the narrow failure window. Repeated attempts to lock a failing DLL (multiple resets) varies the width of this pulse and leads to a successful lock.

Because of the small window of time in which the pulse described may appear, the failure is very intermittent. If the pulse does occur, it might not occur at the next clock transition, but it might occur at some indeterminate time later. Because of this, implementing the work-around is recommended if you use the CLKDV output of the DLL in any of the affected devices.


To address this issue, Xilinx has created a work-around that has been tested and verified against the CLKDV flat-line issue. The work-around provides Verilog code to robustly detect a failure on CLKDV, assert DLL RST, and simultaneously provide customers with a reliable indicator of DLL lock.

You can download the work-around from the following link:


Please follow the "readme.txt" file for full work-around details, implementation instructions, and version information. This work-around uses 36 slices, so it might have a packing impact on highly utilized designs. This work-around has been simulated and tested on silicon and it successfully flags any CLKDV flat-lines (both 0 and 1).
AR# 29845
Date Created 11/28/2007
Last Updated 05/04/2011
Status Active
Type General Article
  • Spartan-II
  • Spartan-IIE
  • Spartan-IIE XA
  • More
  • Virtex
  • Virtex-E
  • Virtex-E QPro
  • Virtex-EM
  • Virtex QPro/R
  • Less