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AR# 29850

9.2i EDK, MPMC v3.00b - ODT signals are asserted one cycle late during a write command

Description

Keyword: one cycle

In a Virtex-4 design with DDR2 memory, the MPMC Core is configured with a certain CAS latency.

When I simulate the design, the ODT signals are asserted one cycle late during a write command. According to the JEDEC specification, there is a two cycle ODT turn-on delay, so in order to align with the write data, the ODT signals should be asserted one cycle earlier than current behavior.


Solution

This issue will be fixed in EDK 10.1, starting with MPMC v4.00.a.

AR# 29850
Date Created 01/03/2008
Last Updated 01/24/2008
Status Active
Type General Article