UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Page Bookmarked

AR# 29921

9.2i EDK SP2 - plbv46_opb_bridge_v1_00_a, SPLB_Clk tied to ground

Description

EDK 9.2 sp1 (EDK_Jm.16+0) does not automatically connect the SPLB_Clk port of the plbv46_opb_bridge peripheral to the attached PLB bus (PLB_Clk). The port is tied to GND, and there are no errors or warnings in PlatGen. The SPLB_Clk does not show up in the filtered PORTS list (System Assembly View).

Solution

Please connect this signal manually to PLB_CLK in the MHS. 

 

The issue has been fixed and is available in EDK 9.2i Service Pack 2 at:  

http://www.xilinx.com/xlnx/xil_sw_updates_home.jsp 

AR# 29921
Date 05/22/2014
Status Archive
Type General Article