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AR# 29948

13.2 EDK - Execution of program hangs on FPU instructions when executed inside an ISR


When an Interrupt Service Routine (ISR) is entered, the Machine-State Register (MSR)is cleared, which clears the Auxiliary Processor Available [bit 6] and Floating-Point Available bits (among others). Consequently, when trying to execute a FPU instruction in the ISR, an exception occurs because the APU is unavailable.


Do not execute FPU instructions in an ISR.

For PPC405, see the "Machine-State Register Following an Interrupt" section in the "Exceptions and Interrupts" chapter of the PowerPC Processor Reference Guide to see the status of the MSR after an interrupt.

For PPC440 , see the "6.3 Interrupt Processing" section and "6.4.1 Machine State Register (MSR)" section in Chapter 6 "Interrupts and Exceptions" of thePPC440x5 CPU CoreUsers Manual (ppc440x5_um.pdf)to see the status of the MSR after an interrupt.
AR# 29948
Date Created 12/14/2007
Last Updated 12/15/2012
Status Active
Type General Article
  • Virtex-5 FXT
  • Virtex-4 FX
  • Virtex-II Pro