UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 29967

9.1i EDK, MPMC2 v1.9 - OPB_toutSup becomes High with first rd/wr on OPB bus

Description

Keyword: MPMC2, v1.9, OPB_toutSup

I configured an OPB PIM for my MPMC2 Core (v1.9). I found that the OPB toutSup signal was being High all the time causing my master peripheral on the OPB to be unable to access the external memory.

Solution

The issue is with the xferAck signal which was never asserted. The xferAck signal is used to reset the toutSup signal.

Work-around #1:

Use MPMC2 v1.8 with the patch in (Xilinx Answer 25146).

Work-around #2:

Add a PLB2OPB and OPB2PLB bridge to bridge to an OPB bus instead of using the OPB PIM.

AR# 29967
Date Created 01/03/2008
Last Updated 12/15/2012
Status Active
Type General Article