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AR# 29968

MIG v2.0 - SL361 board files generate a MAP error, "ERROR:Pack:1107 - Unable to combine the symbols into a single DIFFS component"

Description

The SL361 board files provided with MIG 2.0 include a layout error in which the "cntrl0_ddr_ck[1]" is connected to the N pin and the "cntrl0_ddr_ck_n[1]" is connected to the P pin as follows:

NET "cntrl0_ddr_ck[1]" LOC = "E1" ;

NET "cntrl0_ddr_ck_n[1]" LOC = "E2" ;

These clocks are driven from an OBUFDS in which the O pin should go to the P pin of the FPGA, and the OB pin should go to the N pin of the FPGA. Because of this layout error, the connection is reversed and causes the design to fail during MAP with the following error message:

"ERROR:Pack:1107 - Unable to combine the following symbols into a single DIFFM component:

PAD symbol "cntrl0_ddr_ck[1]" (Pad Signal = cntrl0_ddr_ck[1])

BUFINV symbol "main_00/top0/iobs0/infrastructure_iobs0/r1" (Output Signal = cntrl0_ddr_ck[1])

Each of the following constraints specifies an illegal physical site for a component of type DIFFM:

Symbol "cntrl0_ddr_ck[1]" (LOC=E1 [Physical Site Type = DIFFS])

The component type is determined by the types of logic and the properties and configuration of the logic it contains. Please double check that the types of logic elements and all of their relevant properties and configuration options are compatible with the physical site type of the constraint. Please correct the constraints accordingly.

ERROR:Pack:1107 - Unable to combine the following symbols into a single DIFFS component:

PAD symbol "cntrl0_ddr_ck_n[1]" (Pad Signal = cntrl0_ddr_ck_n[1])

BUFINV symbol "main_00/top0/iobs0/infrastructure_iobs0/r1/N" (Output Signal = cntrl0_ddr_ck_n[1])

Each of the following constraints specifies an illegal physical site for a component of type DIFFS:

Symbol "cntrl0_ddr_ck_n[1]" (LOC=E2 [Physical Site Type = DIFFM])

The component type is determined by the types of logic and the properties and configuration of the logic it contains. Please double check that the types of logic elements and all of their relevant properties and configuration options are compatible with the physical site type of the constraint. Please correct the constraints accordingly."

Solution

To work around this issue, make the following changes to the "infrastructure_iobs_0.vhd" file:

  1. Swap the O and OB outputs of the r1 OBUFDS instance to match with P (E2) and N (E1) pins of the FPGA. The O output generates the ddr_ck_n(1) signal and the OB output generates the signal ddr_ck(1) signal.
  2. Connect the 180 degrees phase-shifted clock to the input I pin of r1.
  3. Generate the 180 degrees phase-shifted clock, ddr1_clk_q(1), from the instance "U1 : FDDRRSE" by reversing the clk0 and clk180 signals to the C1 and C0 inputs.

Following is the code:

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

use work.comp64_parameters_0.all;

library UNISIM;

use UNISIM.VCOMPONENTS.all;

entity comp64_infrastructure_iobs_0 is

port(

ddr_ck : out std_logic_vector((CLK_WIDTH-1) downto 0);

ddr_ck_n : out std_logic_vector((CLK_WIDTH-1) downto 0);

clk0 : in std_logic

);

end comp64_infrastructure_iobs_0;

architecture arc of comp64_infrastructure_iobs_0 is

signal vcc : std_logic;

signal gnd : std_logic;

signal clk180 : std_logic;

signal ddr1_clk_q : std_logic_vector((CLK_WIDTH-1) downto 0);

begin

gnd <= '0';

vcc <= '1';

clk180 <= not clk0;

--- ***********************************

---- This includes instantiation of the output DDR flip flop

---- for ddr clk's and dimm clk's

---- Ouput BUffers for ddr clk's and dimm clk's

---- ***********************************************************

-- original code

-- gen_clk : for i in 0 to CLK_WIDTH-1 generate

-- U0 : FDDRRSE

-- port map (

-- Q => ddr1_clk_q(i),

-- C0 => clk0,

-- C1 => clk180,

-- CE => vcc,

-- D0 => vcc,

-- D1 => gnd,

-- R => gnd,

-- S => gnd

-- );

-- end generate gen_clk;

-- modified code

U0 : FDDRRSE

port map (

Q => ddr1_clk_q(0), -- clk0

C0 => clk0,

C1 => clk180,

CE => vcc,

D0 => vcc,

D1 => gnd,

R => gnd,

S => gnd

);

U1 : FDDRRSE

port map (

Q => ddr1_clk_q(1), -- clk 180

C0 => clk180, // clk180 and clk0 are interchanged to generate 180 degrees phase shifted clock.

C1 => clk0,

CE => vcc,

D0 => vcc,

D1 => gnd,

R => gnd,

S => gnd

);

U2 : FDDRRSE

port map (

Q => ddr1_clk_q(2), -- clk 0

C0 => clk0,

C1 => clk180,

CE => vcc,

D0 => vcc,

D1 => gnd,

R => gnd,

S => gnd

);

U3 : FDDRRSE

port map (

Q => ddr1_clk_q(3), -- clk 0

C0 => clk0,

C1 => clk180,

CE => vcc,

D0 => vcc,

D1 => gnd,

R => gnd,

S => gnd

);

r0 : OBUFDS

port map (

I => ddr1_clk_q(0),

O => ddr_ck(0),

OB => ddr_ck_n(0)

);

r1 : OBUFDS

port map (

I => ddr1_clk_q(1),

O => ddr_ck_n(1), // Interchanged O and OB outputs

OB => ddr_ck(1)

);

r2 : OBUFDS

port map (

I => ddr1_clk_q(2),

O => ddr_ck(2),

OB => ddr_ck_n(2)

);

r3 : OBUFDS

port map (

I => ddr1_clk_q(3),

O => ddr_ck(3),

OB => ddr_ck_n(3)

);

end arc;

This issue is resolved in MIG 2.1.

AR# 29968
Date Created 12/17/2007
Last Updated 12/15/2012
Status Active
Type General Article
Devices
  • Spartan-3
IP
  • MIG
Boards & Kits
  • Spartan-3 Memory Board Development Kit