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AR# 29993

9.2i EDK, MPMC v3.00b - How do I create a dual-rank/dual-DIMM MPMC design? What are the limitations that will cause it to fail?


Keywords: rank, deep, wide, ddr, dimm

How do I create a dual-rank MPMC design? What are the limitations?


As of this writing, MIG does not support the generation of dual rank pinouts. MPMC will support dual-ranks and dual-DIMM memory setups, but will only perform calibration on one rank of one DIMM at this time. Thus dual-rank and dual-DIMM is not recommended for maximum margin. This is described in the MPMC data sheet:

In multi-rank and multi-DIMM systems, the MIG PHY will only calibrate its data capture timing to
one of the ranks on one of the DIMMs. Differences in timing or bus loading affects across ranks and
DIMMs will reduce timing margin and can affect the frequency range of operation.
Note: Multi-rank/multi-DIMM systems are not tested or characterized by MIG. Care must be taken to
ensure that the maximum skew and signal integrity is controlled across ranks and DIMMs.

Note that the required memory initialization will occur on all ranks of all DIMMs. Only the delay choice on the FPGA IDELAYs and read datapath configuration will be adjusted during the calibration phase.

To generate a dual-rank design pinout, first generate a single-rank pinout from MIG, following the MIG and MPMC documentation. Then, add the additional control signal I/Os location constraints as necessary, such as the additional chip-selects. There are few limitations in where these control signals need to be placed, and so anywhere in the same bank as the other control bits will be sufficient. In addition to the location constraints, be sure to add any IOSTANDARD constraints for the new control bits.

Lastly, for the MPMC generation, ensure that the control signal width parameters are set or auto-calculated properly for the specific board connectivity. Adjust the widths of the external ports to match these width parameter settings.

Note: Due to the possibility of failures due to DIMM socket skew and process differences between multiple DIMMs, MPMC no longer allows the use of dual-DIMM designs, starting with EDK 10.1, Service Pack 1.
AR# 29993
Date Created 01/04/2008
Last Updated 02/13/2008
Status Active
Type General Article