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AR# 30020

9.2i EDK, MPMC v3.00b - NCSIM simulation of MPMC does not function correctly, contains 'X' signals

Description

When simulating an EDK system with MPMC using IUS/NCSIM, I find that the MPMC does not accept input after initialization is complete. Undefined states 'X' exist on various init_done signals. The same project simulates correctly in ModelSim. How do I resolve this issue?

Solution

To work around this issue, copy the MPMC_v3_00_b Core to the project pcore directory and modify the hdl/verilog/mpmc_core.v file to have initialization values for all of the InitDone signals starting near Line 1109. Modify to match as follows: 

 

reg PhyIF_Ctrl_InitDone_tmp_d1a = 0; 

// synthesis attribute equivalent_register_removal of PhyIF_Ctrl_InitDone_tmp_d1a is "no" 

reg PhyIF_Ctrl_InitDone_tmp_d1b = 0; 

// synthesis attribute equivalent_register_removal of PhyIF_Ctrl_InitDone_tmp_d1b is "no" 

reg [19:0] PhyIF_Ctrl_InitDone= 20'b00000000000000000000; 

// synthesis attribute equivalent_register_removal of PhyIF_Ctrl_InitDone is "no" 

reg PhyIF_Ctrl_InitDone_270 = 0; 

// synthesis attribute equivalent_register_removal of PhyIF_Ctrl_InitDone_270 is "no" 

reg InitDone = 0; 

// synthesis attribute equivalent_register_removal of InitDone is "no" 

reg InitDone_i = 0; 

// synthesis attribute equivalent_register_removal of InitDone_i is "no" 

reg [C_NUM_PORTS-1:0] InitDone_i2 = 0; 

// synthesis attribute equivalent_register_removal of InitDone_i2 is "no" 

 

 

This is fixed starting in MPMC v4.00.a, to be released in EDK 10.1.

AR# 30020
Date Created 01/08/2008
Last Updated 05/20/2014
Status Archive
Type General Article