| AR# | 30023 |
| Part | IP-RapidIO-Serial |
| Last Modified | 2008-02-15 00:00:00.0 |
| Status | Active |
| Keywords | endpoint, serial, high, speed, high-speed, PHY, logical, design environment, RIO, rapid, IO, MGT, GTP, GTX, I/O, CORE, Generator, physical, logicalio, transport, buffer, channel, bonding, clock, correction, x1, x4, moe_select |
Keywords: endpoint, serial, high, speed, high-speed, PHY, logical, design environment, RIO, rapid, IO, MGT, GTP, GTX, I/O, CORE, Generator, physical, logicalio, transport, buffer, channel, bonding, clock, correction, x1, x4, moe_select
SRIO core operating in x4 mode cannot train down to x1 mode if lane 0 has been disconnected. This is applicable to Virtex-5, Virtex-4 and Virtex-II Pro families. The core will be able to train down to x1 mode on lane 0, but it will not be able to train down to any other lanes. This is due to attribute CHAN_BOND_MODE = "slave" set on transceivers of lane 1, 2 and 3. The transceiver on lane 0 has CHAN_BOND_MODE = "master".