AR #30023 - LogiCORE RapidIO - Core cannot train down to x1 mode if lane 0 is disconnected

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LogiCORE RapidIO - Core cannot train down to x1 mode if lane 0 is disconnected

AR# 30023
Part IP-RapidIO-Serial
Last Modified 2008-02-15 00:00:00.0
Status Active
Keywords endpoint, serial, high, speed, high-speed, PHY, logical, design environment, RIO, rapid, IO, MGT, GTP, GTX, I/O, CORE, Generator, physical, logicalio, transport, buffer, channel, bonding, clock, correction, x1, x4, moe_select

Description

Keywords: endpoint, serial, high, speed, high-speed, PHY, logical, design environment, RIO, rapid, IO, MGT, GTP, GTX, I/O, CORE, Generator, physical, logicalio, transport, buffer, channel, bonding, clock, correction, x1, x4, moe_select

SRIO core operating in x4 mode cannot train down to x1 mode if lane 0 has been disconnected. This is applicable to Virtex-5, Virtex-4 and Virtex-II Pro families. The core will be able to train down to x1 mode on lane 0, but it will not be able to train down to any other lanes. This is due to attribute CHAN_BOND_MODE = "slave" set on transceivers of lane 1, 2 and 3. The transceiver on lane 0 has CHAN_BOND_MODE = "master".

Solution

Please see (Xilinx Answer 30042) for detail of transceiver issue and the work-around.

 
 
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